1. Field of the Invention
The present invention relates to a successive approximation analog-to-digital converter (hereinafter, referred to as an SAR ADC), and more particularly, to an SAR ADC having small capacitance and a small circuit area while having strong process change resistance characteristics.
2. Description of the Related Art
Most communication systems receive analog signals, digitally process the analog signals, convert the digitally processed signals into analog form, and output the signals converted into analog form.
Therefore, most communication systems essentially include an analog-to-digital signal converter and a digital-to-analog signal converter. The analog-to-digital signal converter is positioned at the first stage of the communication system to determine a signal to noise ratio (SNR) of an entire system. As a result, a designer is required to pay the most attention to the design of an analog block and to also pay attention to a power consumption block.
The SAR ADC is a type of analog-to-digital signal converter. The SAR ADC is mainly used as a relatively medium/slow speed data converter and has the characteristic of relatively small power consumption.
FIG. 1 is a diagram showing an SAR ADC according to the related art.
As shown in FIG. 1, the SAR ADC according to the related art includes a plurality of capacitors 4C, 2C, and C having binary scale capacitance and performs a binary search by the size ratio of the plurality of capacitors 4C, 2C, and C, thereby performing data conversion.
In the case of the SAR ADC of FIG. 1, the resolution of the SAR ADC is determined as the size ratio of each capacitor. When there is an error in the size ratio of the plurality of capacitors 4C, 2C, and C due to process change, the resolution of the entire SAR ADC is significantly deteriorated.
Since the capacitor occupying a relatively large area should be provided in plural, there is a problem in that the capacitance and the circuit area of the SAR ADC are also increased. For example, in order to obtain a resolution of 10 bits, a capacitance and a circuit area of up to 1024 times more than a unit capacitor are required. This causes a large RC time constant, which takes a very long time to stabilize the signal in each step. Therefore, it is difficult to perform high-speed sampling and conversion by using the SAR ADC according to the related art.
If the unit capacitor is minimized, the sampling and conversion speed can be improved; however, when the size of the unit capacitor is small, the incidence of process errors is greatly increased and thus, the SAR ADC should basically use a large capacitor.